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INTEGRATED CIRCUITS
DATA SHEET
UDA1344TS Low-voltage low-power stereo audio CODEC with DSP features
Preliminary specification Supersedes data of 2000 Jan 27 File under Integrated Circuits, IC01 2000 Feb 04
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
FEATURES General * Low power consumption * 3.0 V power supply * System clock of 256fs, 384fs and 512fs * Supports sampling frequencies from 8 to 55 kHz * Non-inverting ADC plus integrated high-pass filter to cancel DC offset * ADC supports 2 V (RMS) input signals * Overload detector for easy record level control * Separate power control for ADC and DAC * Integrated digital interpolation filter plus non-inverting DAC * Functions controllable either via L3 microcontroller interface or via static pins * UDA1344TS is pin and function compatible with UDA1340M * Small package size (SSOP28) * Easy application. Multiple format input interface * I2S-bus, MSB-justified or LSB-justified 16, 18 and 20 bits format compatible * Three combined data formats with MSB-justified output and LSB-justified 16, 18 and 20 bits input * 1fs input and output format data rate. DAC digital sound processing The sound processing features of the UDA1344TS can be used in the L3 mode only: * Digital tone control, bass boost and treble * Digital dB-linear volume control (low microcontroller load) via L3 microcontroller * Digital de-emphasis for 32, 44.1 and 48 kHz * Soft mute. ORDERING INFORMATION TYPE NUMBER UDA1344TS PACKAGE NAME SSOP28 DESCRIPTION Advanced audio configuration
UDA1344TS
* Stereo single-ended input configuration * Stereo line output (under microcontroller volume control), no post filter required * High linearity, dynamic range and low distortion. GENERAL DESCRIPTION The UDA1344TS is a single-chip stereo Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with signal processing features employing bitstream conversion techniques. The low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates recording and playback functions. The UDA1344TS supports the I2S-bus data format with word lengths of up to 20 bits, the MSB-justified data format with word lengths of up to 20 bits and the LSB-justified data format with word lengths of 16, 18 and 20 bits. The UDA1344TS also supports three combined data formats with MSB-justified data output and LSB-justified 16, 18 and 20 bits data input. The UDA1344TS can be controlled either via static pins or via the L3 interface. In the L3 mode the UDA1344TS has special Digital Sound Processing (DSP) features in playback mode such as de-emphasis, volume control, bass boost, treble and soft mute.
VERSION SOT341-1
plastic shrink small outline package; 28 leads; body width 5.3 mm
2000 Feb 04
2
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
QUICK REFERENCE DATA SYMBOL Supplies VDDA(ADC) VDDA(DAC) VDDO VDDD IDDA(ADC) IDDA(DAC) IDDO IDDD ADC analog supply voltage DAC analog supply voltage operational amplifier supply voltage digital supply voltage ADC analog supply current DAC analog supply current operational amplifier supply current digital supply current operating ADC power-down operating DAC power-down operating DAC power-down operating DAC power-down ADC power-down Tamb Vi(rms) (THD + N)/S S/N cs Vo(rms) (THD + N)/S S/N cs PADDA PDA PAD PPD Notes ambient temperature Analog-to-digital converter input voltage (RMS value) total harmonic distortion-plus-noise to signal ratio signal-to-noise ratio channel separation notes 1 and 2 at 0 dB at -60 dB; A-weighted Vi = 0 V; A-weighted - - - - - notes 3 and 4 at 0 dB at -60 dB; A-weighted code = 0; A-weighted - - - - - - - - - 1.0 2.7 2.7 2.7 2.7 - - - - - - - - - -40 PARAMETER CONDITIONS MIN.
UDA1344TS
TYP.
MAX.
UNIT
3.0 3.0 3.0 3.0 9.0 3.5 4.0 25 4.0 250 6.0 2.5 3.5 -
3.6 3.6 3.6 3.6 11.0 5.0 6.0 75 6.0 350 9.0 4.0 5.0 +85 - -80 -30 - - - -85 - - - - - - -
V V V V mA mA mA A mA A mA mA mA C V dB dB dB dB
-85 -35 95 100
Digital-to-analog converter output voltage (RMS value) total harmonic distortion-plus-noise to signal ratio signal-to-noise ratio channel separation 900 -90 -37 100 100 mV dB dB dB dB
Power performance power consumption in record and playback mode power consumption in playback mode power consumption in record mode power consumption in power-down mode 69 42 37.5 17 mW mW mW mW
1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series resistor. 2. The input voltage to the ADC is inversely proportional to the supply voltage. 3. The output voltage of the UDA1344TS differs from the output voltage of the UDA1340M. 4. The output of the DAC scales proportionally with the supply voltage. 2000 Feb 04 3
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
BLOCK DIAGRAM
UDA1344TS
handbook, full pagewidth
VDDA(ADC) VSSA(ADC) 2 1
VADCP 7
VADCN 6
Vref(A) 4
3 VINL
0 dB/6 dB SWITCH
0 dB/6 dB SWITCH
5
VINR
ADC
ADC 8 MC1 MC2 MP5
VDDD VSSD
10 11
DECIMATION FILTER
21 20
DC-CANCELLATION FILTER 18 16 17 19 DIGITAL INTERFACE L3-BUS INTERFACE 13 14 15 12
DATAO BCK WS DATAI
MP2 MP3 MP4 SYSCLK
MP1
9
DSP FEATURES
INTERPOLATION FILTER
UDA1344TS
NOISE SHAPER
DAC
DAC
VOUTL
26
24
VOUTR
25 VDDO
27 VSSO
23 VDDA(DAC)
22 VSSA(DAC)
28 Vref(D)
MGL441
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
PINNING SYMBOL VSSA(ADC) VDDA(ADC) VINL Vref(A) VINR VADCN VADCP MC1 MP1 VDDD VSSD SYSCLK MP2 MP3 MP4 BCK WS DATAO DATAI MP5 MC2 VSSA(DAC) VDDA(DAC) VOUTR VDDO VOUTL VSSO Vref(D) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DESCRIPTION ADC analog ground ADC analog supply voltage ADC input left ADC reference voltage ADC input right ADC negative reference voltage ADC positive reference voltage mode control 1 input (pull-down) multi purpose pin 1 output digital supply voltage digital ground system clock input: 256fs, 384fs or 512fs multi purpose pin 2 input multi purpose pin 3 input multi purpose pin 4 input bit clock input word select input data output data input multi purpose pin 5 output (pull-down) mode control 2 input (pull-down) DAC analog ground DAC analog supply voltage DAC output right operational amplifier supply voltage DAC output left operational amplifier ground DAC reference voltage
handbook, halfpage
UDA1344TS
VSSA(ADC) 1 VDDA(ADC) 2 VINL 3 Vref(A) 4 VINR 5 VADCN 6 VADCP 7 MC1 8 MP1 9 VDDD 10 VSSD 11 SYSCLK 12 MP2 13 MP3 14
MGL442
28 Vref(D) 27 VSSO 26 VOUTL 25 VDDO 24 VOUTR 23 VDDA(DAC)
UDA1344TS
22 VSSA(DAC) 21 MC2 20 MP5 19 DATAI 18 DATAO 17 WS 16 BCK 15 MP4
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
FUNCTIONAL DESCRIPTION The UDA1344TS accommodates slave mode only, this means that in all applications the system devices must provide the system clock. The system clock must be locked in frequency to the digital interface input signals. The BCK clock can be up to 128fs, or in other words the BCK frequency is 128 times the Word Select (WS) frequency or less: fBCK = < 128 x fWS. Remarks: 1. The WS edge MUST fall on the negative edge of the BCK clock at all times for proper operation of the digital I/O data interface 2. The sampling frequency range is from 5 to 55 kHz 3. For MSB- and LSB-justified formats it is important to have a WS signal with a duty factor of 50%. Analog-to-Digital Converter (ADC) The stereo ADC of the UDA1344TS consists of two 3rd-order Sigma-Delta modulators. They have a modified Ritchie-coder architecture in a differential switched capacitor implementation. The oversampling ratio is 128. In contrast to the UDA1340M, the UDA1344TS supports 1 V (RMS) input signals and can be set, via an external resistor, to support 2 V (RMS) input signals. Analog front-end The analog front-end is equipped with a selectable 0 dB or 6 dB gain block. The pin to select the gain switch is given in Section "L3 mode". This block can be used in applications in which both 1 V (RMS) and 2 V (RMS) input signals are available. In applications in which a 2 V (RMS) input signal is used, a 12 k resistor must be connected in series with the input of the ADC. This makes a voltage divider with the internal ADC resistor and makes sure only 1 V (RMS) maximum is input to the IC. Using this application for a 2 V (RMS) input signal, the gain switch must be set to 0 dB. When a 1 V (RMS) input signal is input to the ADC in the same application, the gain switch must be set to 6 dB. An overview of the maximum input voltages allowed against the presence of an external resistor and the setting of the gain switch is given in Table 1. Decimation filter (ADC) Table 1
UDA1344TS
Application modes using input gain stage INPUT GAIN SWITCH 0 dB 6 dB 0 dB 6 dB MAXIMUM INPUT VOLTAGE 2 V (RMS) 1 V (RMS) 1 V (RMS) 0.5 V (RMS)
RESISTOR (12 k) Present Present Absent Absent
The decimation from 128fs to 1fs is performed in 2 stages. sin x The first stage realizes 3rd-order ----------- characteristic. This x filter decreases the sample rate by 16. The second stage, a Finite Impulse Response (FIR) filter, consists of 3 half-band filters, each decimating by a factor of 2. Table 2 Decimation filter characteristics CONDITIONS 0 - 0.45fs >0.55fs 0 - 0.45fs DC VALUE (dB) 0.05 -60 108 -1.16
ITEM Pass-band ripple Stop band Dynamic range Overall gain with 0 dB input to the ADC
DC-cancellation filter (ADC) An optional Infinite Impulse-Response (IIR) high-pass filter is provided to remove unwanted DC components. The operation is selected by the microcontroller via the L3 interface. The filter characteristics are given in Table 3. Table 3 DC-cancellation filter characteristics ITEM Pass-band ripple Pass-band gain Droop Attenuation at DC Dynamic range CONDITIONS - - at 0.00045fs at 0.00000036fs 0 - 0.45fs VALUE (dB) none 0 0.031 >40 >110
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
Mute (ADC) On recovery from power-down or switching on of the system clock, the serial data output on pin DATAO is held at LOW level until valid data is available from the decimation filter. This time depends on whether the DC-cancellation filter is selected: * DC cancel off: 1024 t = ------------ ; t = 23.2 ms at fs = 44.1 kHz fs * DC cancel on: 12288 t = --------------- ; t = 279 ms at fs = 44.1 kHz. fs Interpolation filter (DAC) The digital filter interpolates from 1fs to 128fs by means of a cascade of a recursive filter and an FIR filter. Table 4 Interpolation filter characteristics CONDITIONS 0 - 0.45fs >0.55fs 0 - 0.45fs DC VALUE (dB) 0.03 -50 108 -3.5
UDA1344TS
Multiple format input/output interface The UDA1344TS supports the following data input/output formats: * I2S-bus format with data word length of up to 20 bits * MSB-justified serial format with data word length of up to 20 bits * LSB-justified serial format with data word lengths of 16, 18 or 20 bits (in L3 mode only) * Combined data formats: - L3 mode: MSB-justified data output and LSB-justified 16, 18 and 20 bits data input - Static pin mode: MSB-justified data output and LSB-justified 16 and 20 bits data input. The formats are illustrated in Fig.3. Left and right data-channel words are time multiplexed. Control mode selection The UDA1344TS can be used under L3 microcontroller interface control or static pin control. The mode can be set via the mode control pins MC1 and MC2 (see Table 5). Table 5 Mode control pins PIN MC1 LOW HIGH LOW HIGH Static pin mode MODE L3 mode Test mode
ITEM Pass-band ripple Stop band Dynamic range Gain Noise shaper (DAC)
PIN MC2 LOW LOW HIGH HIGH
The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream Digital-to-Analog Converter (FSDAC). Filter stream DAC The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC scales proportionally with the power supply voltage.
Important: in the L3 mode the UDA1344TS is completely pin and function compatible with the UDA1340M.
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dbook, full pagewidth
2000 Feb 04
WS 1 BCK 2 3 LEFT >=8 1 2 3 DATA MSB B2 MSB B2 I2S-BUS FORMAT WS 1 BCK 2 LEFT 3 >=8 1 2 DATA MSB B2 LSB MSB B2 WS LEFT BCK
Philips Semiconductors
Low-voltage low-power stereo audio CODEC with DSP features
RIGHT >=8
MSB
RIGHT 3 >=8
LSB
MSB
B2
MSB-JUSTIFIED FORMAT
RIGHT 16 15 2 1 16 15 2 1
8
DATA
MSB
B2
B15 LSB LSB-JUSTIFIED FORMAT 16 BITS
MSB
B2
B15 LSB
WS
LEFT 18 17 16 15 2 1
RIGHT 18 17 16 15 2 1
BCK
DATA
MSB
B2
B3
B4
B17 LSB LSB-JUSTIFIED FORMAT 18 BITS
MSB
B2
B3
B4
B17 LSB
WS
LEFT 20 19 18 17 16 15 2 1
RIGHT 20 19 18 17 16 15 2 1
BCK
Preliminary specification
DATA
MSB
B2
B3
B4
B5
B6
B19 LSB LSB-JUSTIFIED FORMAT 20 BITS
MSB
B2
B3
B4
B5
B6
B19 LSB
MBL140
UDA1344TS
Fig.3 Serial interface formats.
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
Static pin mode The UDA1344TS is set to static pin mode by setting both pins MC1 and MC2 to HIGH level. The controllable features in this mode are: * System clock frequency selection * Data input/output format selection * De-emphasis and mute control * Power-down and ADC input level selection. PINNING DEFINITION The pinning definition in the static pin mode is given in Table 6. Table 6 Pinning definition in static pin model PIN MP1 MP2 MP3 MP4 DESCRIPTION data input/output setting three-level pin to select no de-emphasis, de-emphasis or mute 256fs or 384fs system clock selection three-level pin to select ADC power-down, ADC input 1 V (RMS) or ADC input 2 V (RMS) data input/output setting HIGH HIGH MUTE AND DE-EMPHASIS
UDA1344TS
The level definition of pin MP2 pin is given in Table 8. Table 8 Levels for pin MP2 SELECTION no de-emphasis and mute de-emphasis 44.1 kHz mute
PIN MP2 LOW 0.5VDDD HIGH
INPUT/OUTPUT DATA FORMAT SELECTION The input/output data format can be selected using pins MP1 and MP5 as given in Table 9. Table 9 Data format selection SELECTION input: MSB-justified input: I2S-bus input: LSB-justified 20 bits; output: MSB-justified input: LSB-justified 16 bits; output: MSB-justified
PIN MP1 PIN MP5 LOW LOW HIGH LOW HIGH LOW
MP5 SYSTEM CLOCK
ADC INPUT VOLTAGE SELECTION AND POWER-DOWN In the static pin mode the three-level pin MP4 is used to select 0 or 6 dB gain and power-down. Table 10 Levels for pin MP4 PIN MP4 SELECTION ADC power-down 6 dB gain 0 dB gain
In the static pin mode the options are 256fs and 384fs as given in Table 7. Table 7 System clock selection SELECTION 256fs clock frequency 384fs clock frequency
LOW 0.5VDDD HIGH
PIN MP3 LOW HIGH
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
L3 mode The UDA1344TS is set to the L3 mode by setting both pins MC1 and MC2 to LOW level. The static pins in this mode are used for: * ADC output overload detection * L3 interface signal input * ADC input voltage selection. The controllable features via the L3 interface and the definition of the control registers are given in Section "L3 interface". PINNING DEFINITION The pinning definition in the L3 mode is given in Table 11. Table 11 Pinning definition in L3 mode PIN MP1 MP2 MP3 MP4 MP5 FUNCTION ADC output overload detection L3MODE input L3CLOCK input L3DATA input ADC input voltage selection: 1 V (RMS) or 2 V (RMS) ADC OUTPUT OVERLOAD DETECTION
UDA1344TS
In practice the output is used to indicate whenever the output data, in either the left or right channel, is greater than -1 dB (actual figure is -1.16 dB) of the maximum possible digital swing. When this condition is detected pin MP1 is forced to HIGH level for at least 512fs cycles (11.6 ms at fs = 44.1 kHz). This time-out is reset for each infringement. ADC INPUT VOLTAGE SELECTION In the L3 mode pin MP5 is used to select 0 or 6 dB gain. Table 12 Levels for pin MP5 PIN MP4 LOW HIGH 0 dB gain 6 dB gain SELECTION
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
L3 INTERFACE The UDA1344TS has a microcontroller input mode. In the microcontroller control mode, all the digital sound processing features and the system controlling features can be controlled by the microcontroller. The controllable features are: * System clock frequency * Data input format * Power control * DC filtering * De-emphasis * Volume * Flat/min./max. switch * Bass boost * Treble * Mute. The exchange of data and control information between the microcontroller and the UDA1344TS is accomplished through a serial hardware interface comprising the following lines: L3DATA: microcontroller interface data line L3MODE: microcontroller interface mode line L3CLOCK: microcontroller interface clock line. Information transfer via the microcontroller bus is LSB first and is organized in accordance with the so called `L3' format, in which two different modes of operation can be distinguished: address mode and data transfer mode. The address mode is required to select a device communicating via the L3 interface and to define the destination registers for the data transfer mode. Data transfer for the UDA1344TS can only be in one direction: input to the UDA1344TS to program its sound processing and other functional features. Address mode The address mode is used to select a device for subsequent data transfer and to define the destination registers. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 data bits. The fundamental timing is shown in Fig.4. Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the UDA1344TS is 000101 (bits 7 to 2). 1 1 0 1 1 0
UDA1344TS
Data bits 1 and 0 indicate the type of subsequent data transfer as given in Table 13. Table 13 Selection of data transfer BIT 1 0 BIT 0 0 TRANSFER data (volume, bass boost, treble, de-emphasis, mute, mode and power control) not used status (system clock frequency, data input/output format and DC filter) not used
In the event that the UDA1344TS receives a different address, it will deselect its microcontroller interface logic. Data transfer mode The selection preformed in the address mode remains active during subsequent data transfers, until the UDA1344TS receives a new address command. The fundamental timing of data transfers is essentially the same as in the address mode and is shown in Fig.5. The maximum input clock and data rate is 64fs. All transfers are byte wise, i.e. they are based on groups of 8 bits. Data will be stored in the UDA1344TS after the eighth bit of a byte has been received. A multibyte data transfer is illustrated in Fig.6. Programming the sound processing and other features The sound processing and other feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred. This is performed in the address mode by bit 1 and bit 0 (see Table 13). The second selection is performed by the 2 MSBs of the data byte (bit 7 and bit 6). The other bits in the data byte (bits 5 to 0) is the value that is placed in the selected registers.
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
UDA1344TS
handbook, full pagewidth
L3MODE th(L3)A tCLK(L3)L tsu(L3)A L3CLOCK tCLK(L3)H th(L3)A tsu(L3)A
Tcy(CLK)(L3) tsu(L3)DA th(L3)DA
L3DATA
BIT 0
BIT 7
MGL723
Fig.4 Timing in address mode.
handbook, full pagewidth
tstp(L3)
tstp(L3)
L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D
L3CLOCK
tsu(L3)DA
th(L3)DA
L3DATA WRITE
BIT 0
BIT 7
MGL882
Fig.5 Timing in data transfer mode.
2000 Feb 04
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
UDA1344TS
handbook, full pagewidth
tstp(L3)
L3MODE
L3CLOCK
L3DATA
address
data byte #1
data byte #2
address
MGL725
Fig.6 Multibyte data transfer.
L3 interface registers When the data transfer of type `status' is selected, the features system clock frequency, data input format and DC filter can be controlled. Table 14 Data transfer of type `status' BIT 7 0 BIT 6 0 BIT 5 SC1 BIT 4 SC0 BIT 3 IF2 BIT 2 IF1 BIT 1 IF0 BIT 0 DC REGISTER SELECTED SC = system clock frequency (2 bits); see Table 16 IF = data input format (3 bits); see Table 17 DC = DC filter (1 bit); see Table 18 When the data transfer of type `data' is selected, the features volume, bass boost, treble, de-emphasis, mute, mode and power control can be controlled. Table 15 Data transfer of type `data' BIT 7 0 0 1 BIT 6 0 1 0 BIT 5 VC5 BB3 0 BIT 4 VC4 BB2 DE1 BIT 3 VC3 BB1 DE0 BIT 2 VC2 BB0 MT BIT 1 VC1 TR1 M1 BIT 0 VC0 TR0 M0 REGISTER SELECTED VC = volume control (6 bits); see Table 19 BB = bass boost (4 bits); see Table 20 TR = treble (2 bits); see Table 21 DE = de-emphasis (2 bits); see Table 22 MT = mute (1 bit); see Table 23 M = filter mode (2 bits); see Table 24 1 1 0 0 0 0 PC1 PC0 PC = power control (2 bits); see Table 25
2000 Feb 04
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
SYSTEM CLOCK FREQUENCY A 2-bit value to select the used external clock frequency. Table 16 System clock frequency settings SC1 0 0 1 1 DATA INPUT FORMAT A 3-bit value to select the used data format. Table 17 Data format settings IF2 0 0 0 0 1 1 1 1 IF1 0 0 1 1 0 0 1 1 IF0 0 1 0 1 0 1 0 1 I2S-bus LSB-justified 16 bits LSB-justified 18 bits LSB-justified 20 bits MSB-justified input: LSB-justified 16 bits; output: MSB-justified input: LSB-justified 18 bits; output: MSB-justified input: LSB-justified 20 bits; output: MSB-justified BASS BOOST FORMAT SC0 0 1 0 1 512fs 384fs 256fs not used SELECTION Table 19 Volume settings VOLUME CONTROL
UDA1344TS
A 6-bit value to program the left and right channel volume attenuation. The range is from 0 to - dB in steps of 1 dB.
VC5 VC4 VC3 VC2 VC1 VC0 0 0 0 0 : 1 1 1 1 1 0 0 0 0 : 1 1 1 1 1 0 0 0 0 : 1 1 1 1 1 0 0 0 0 : 0 1 1 1 1 0 0 1 1 : 1 0 0 1 1 0 1 0 1 : 1 0 1 0 1
VOLUME (dB) 0 0 -1 -2 : -58 -59 -60 - -
A 4-bit value to program the bass boost setting. The used set depends on the mode bits M1 and M0. Table 20 Bass boost settings BASS BOOST SETTING BB3 BB2 BB1 BB0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FLAT (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIN. (dB) 0 2 4 6 8 10 12 14 16 18 18 18 18 18 18 18 MAX. (dB) 0 2 4 6 8 10 12 14 16 18 20 22 24 24 24 24
DC FILTER A 1-bit value to enable the digital DC filter. Table 18 DC filtering DC 0 1 SELECTION no DC filtering DC filtering
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
TREBLE A 2-bit value to program the treble setting. The used set depends on the mode bits M1 and M0. Table 21 Treble settings TREBLE SETTING TR1 0 0 1 1 DE-EMPHASIS A 2-bit value to enable the digital de-emphasis filter. Table 22 De-emphasis settings DE1 0 0 1 1 MUTE A 1-bit value to enable the digital mute. Table 23 Mute MT 0 1 no muting muting SELECTION DE0 0 1 0 1 SELECTION no de-emphasis de-emphasis 32 kHz de-emphasis 44.1 kHz de-emphasis 48 kHz 0 0 1 1 0 1 0 1 TR0 FLAT (dB) 0 1 0 1 0 0 0 0 MIN. (dB) 0 2 4 6 MAX. (dB) 0 2 4 6 MODE
UDA1344TS
A 2-bit value to program the mode of the sound processing filters of bass boost and treble. Table 24 Flat/min./max. switch M1 0 0 1 1 POWER CONTROL A 2-bit value to disable the ADC and/or DAC to reduce power consumption. Table 25 Power control settings SELECTION PC1 PC0 ADC off off on on DAC off on off on M0 0 1 0 1 flat min. min. max. SELECTION
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDDD Txtal(max) Tstg Tamb Ves digital supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic handling voltage note 1 note 2 Notes 1. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor. 2. Equivalent to discharging a 200 pF capacitor via a 2.5 H series inductor. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air PARAMETER CONDITIONS
UDA1344TS
MIN. - - -65 -40 -300
MAX. 5.0 150 +125 +85 +300
UNIT V C C C V
-3000 +3000 V
VALUE 90
UNIT K/W
DC CHARACTERISTICS VDDD = VDDA = VDDO = 3.0 V; Tamb = 25 C; RL = 5 k; all voltages referenced to ground; unless otherwise specified. SYMBOL Supplies; note 1 VDDA(ADC) ADC analog supply voltage VDDA(DAC) DAC analog supply voltage VDDO VDDD IDDA(ADC) IDDA(DAC) IDDO IDDD operational amplifier supply voltage digital supply voltage ADC analog supply current DAC analog supply current operating ADC power-down operating DAC power-down operational amplifier supply current operating DAC power-down digital supply current operating DAC power-down ADC power-down Digital inputs VIH VIL ILI Ci HIGH-level input voltage LOW-level input voltage input leakage current input capacitance 0.8VDDD -0.5 - - - - - - VDDD + 0.5 0.2VDDD 10 10 V V A pF 2.7 2.7 2.7 2.7 - - - - - - - - - 3.0 3.0 3.0 3.0 9.0 3.5 4.0 25 4.0 250 6.0 2.5 3.5 3.6 3.6 3.6 3.6 11.0 5.0 6.0 75 6.0 300 9.0 4.0 5.0 V V V V mA mA mA A mA A mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
SYMBOL Digital outputs VOH VOL VIH VIM VIL Vref(A) Ro(refA) Ri Ci Vref(D) Ro(refD) Ro Io(max) RL CL Notes HIGH-level output voltage LOW-level output voltage IOH = -2 mA IOL = 2 mA 0.85VDDD - 0.9VDDD 0.4VDDD -0.5 referenced to VSSA(ADC) fi = 1 kHz 0.45VDDA - - - referenced to VSSA(DAC) 0.45VDDA - - (THD + N)/S < 0.1 - %; RL = 5 k 3 note 2 - - - - - - 0.5VDDA 24 9.8 20 - 0.4 PARAMETER CONDITIONS MIN. TYP.
UDA1344TS
MAX.
UNIT
V V
Three-level inputs: pins MP2 and MP4 HIGH-level input voltage MIDDLE-level input voltage LOW-level input voltage VDDD + 0.5 0.6VDDD 0.1VDDD 0.55VDDA - - - 0.55VDDA - 3.0 - - 200 V V V
Analog-to-digital converter reference voltage output resistance on pin Vref(A) input resistance input capacitance V k k pF
Digital-to-analog converter reference voltage output resistance on pin Vref(D) output resistance of DAC maximum output current load resistance load capacitance 0.5VDDA 28 0.13 0.22 - - V k mA k pF
1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 2. When higher capacitive loads must be driven, a 100 resistor must be connected in series with the DAC output in order to prevent oscillations in the output operational amplifier.
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
UDA1344TS
AC CHARACTERISTICS VDDD = VDDA = VDDO = 3.0 V; fi = 1 kHz; Tamb = 25 C; RL = 5 k; all voltages referenced to ground; unless otherwise specified. SYMBOL Analog-to-digital converter Vi(rms) Vi (THD + N)/S S/N cs PSRR input voltage (RMS value) unbalance between channels total harmonic distortion-plus-noise to signal ratio at 0 dB at -60 dB; A-weighted signal-to-noise ratio channel separation power supply rejection ratio fripple = 1 kHz; Vripple = 300 mV (p-p) notes 3 and 4 Vi = 0 V; A-weighted notes 1 and 2 1.0 0.1 -85 -35 95 100 30 - - -80 -30 - - - V dB dB dB dB dB dB PARAMETER CONDITIONS TYP. MAX. UNIT
Digital-to-analog converter Vo(rms) Vo (THD + N)/S S/N cs PSRR Notes 1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series resistor. 2. The input voltage to the ADC is inversely proportional with the supply voltage. 3. The output voltage of the UDA1344TS differs from the output voltage of the UDA1340M. 4. The output of the DAC scales proportionally with the supply voltage. output voltage (RMS value) unbalance between channels total harmonic distortion-plus-noise to signal ratio at 0 dB at -60 dB; A-weighted signal-to-noise ratio channel separation power supply rejection ratio fripple = 1 kHz; Vripple = 300 mV (p-p) code = 0; A-weighted 900 0.1 -90 -37 100 100 50 - - -85 - - - - mV dB dB dB dB dB dB
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
UDA1344TS
TIMING VDDD = VDDA = VDDO = 2.7 to 3.6 V; Tamb = -40 to +85 C; RL = 5 k; all voltages referenced to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
System clock input (see Fig.7) Tsys system clock cycle time fsys = 256fs fsys = 384fs fsys = 512fs tCWH tCWL system clock HIGH time system clock LOW time fsys < 19.2 MHz fsys 19.2 MHz fsys < 19.2 MHz fsys 19.2 MHz Serial interface input/output data (see Fig.8) fBCK Tcy(BCK) tBCKH tBCKL tr tf tsu(WS) th(WS) tsu(DATAI) th(DATAI) th(DATAO) td(DATAO-WS) bit clock frequency bit clock cycle time bit clock HIGH time bit clock LOW time rise time fall time word select set-up time word select hold time data input set-up time data input hold time data output hold time data output to word select delay from WS edge for MSB-justified format Tcy(s) = cycle time of sample frequency - T cy(s) -----------64 100 100 - - 20 10 20 0 0 from BCK falling edge - - - - - - - - - - - - - - - 64fs - - - 20 20 - - - - - 80 80 Hz ns ns ns ns ns ns ns ns ns ns ns ns 78 52 39 88 59 44 262 174 132 ns ns ns
0.30Tsys - 0.40Tsys - 0.30Tsys - 0.40Tsys -
0.70Tsys ns 0.60Tsys ns 0.70Tsys ns 0.60Tsys ns
td(DATAO-BCK) data output to bit clock delay
L3 interface input (see Figs 4 and 5) Tcy(CLK)L3 tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)D th(L3)D tstp(L3) tsu(L3)DA th(L3)DA L3CLOCK cycle time L3CLOCK HIGH time L3CLOCK LOW time L3MODE set-up time for address mode L3MODE hold time for address mode L3MODE set-up time for data transfer mode L3MODE hold time for data transfer mode L3MODE stop time L3DATA set-up time in data transfer and address mode L3DATA hold time in data transfer and address mode 19 500 250 250 190 190 190 190 190 190 30 - - - - - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns
2000 Feb 04
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
UDA1344TS
handbook, full pagewidth
tCWH
tCWL Tsys
MGL443
Fig.7 System clock timing.
handbook, full pagewidth
WS t BCKH t h(WS) t su(WS) BCK t BCKL Tcy(BCK) DATAO t d(DATAO-BCK)
tr
tf
t d(DATAO-WS)
t h(DATAO)
t su(DATAI) t h(DATAI) DATAI
MGS756
Fig.8 Serial interface timing.
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
APPLICATION INFORMATION
UDA1344TS
handbook, full pagewidth
L1 3V 8LM32A07 L2 8LM32A07 ground C12 100 F (16 V) VDD2 C11 100 F (16 V) C2 100 F (16 V) C21 100 nF (63 V) VDD1
VDD1 R21 1
VDD2 R28 1
R24 10
C9 100 F (16 V)
C25 100 nF (63 V) VADCN 7 VADCP
C29 100 nF (63 V) VSSD 11
VSSA(ADC) VDDA(ADC) system clock R30 47 DATAO BCK WS DATAI SYSCLK 1 12 2 6
VDDD 10
18 16 17 19
4
Vref(A) C22 100 nF (63 V) C3 47 F (16 V)
overload flag
MP1
9 26
VOUTL
C5 47 F (16 V) R22 10 k
R23 100
X2
left output
left input
X4
C1 47 F (16 V)
VINL
3
UDA1344TS
24 right input X5 C6 47 F (16 V) MP2 MP3 MP4 13 14 15 27 VSSO C26 100 nF (63 V) C7 100 F (16 V) 25 VDDO 22 VSSA(DAC) C27 100 nF (63 V) C10 100 F (16 V) 23 VDDA(DAC) VINR 5
VOUTR
C8 R27 10 k
R26 100
X3
47 F (16 V)
right output
28
Vref(D) C23 100 nF (63 V) C4 47 F (16 V)
MGL444
R25 1 VDD1
R29 1 VDD1
Fig.9 Application diagram.
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
UDA1344TS
SOT341-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 14 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 8 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150 EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 99-12-27
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Manual soldering
UDA1344TS
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
Suitability of surface mount IC packages for wave and reflow soldering methods
UDA1344TS
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
NOTES
UDA1344TS
2000 Feb 04
25
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
NOTES
UDA1344TS
2000 Feb 04
26
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
NOTES
UDA1344TS
2000 Feb 04
27
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/25/03/pp28
Date of release: 2000
Feb 04
Document order number:
9397 750 06836

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